1. Field of the Invention
The present invention relates generally to semiconductor manufacturing. More specifically, the present invention relates to chemical mechanical planarization.
2. Description of the Related Art
In the fabrication of semiconductor devices, planarization operations are often performed on a semiconductor wafer (“wafer”) to provide polishing, buffing, and cleaning effects. Typically, the wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Patterned conductive layers are insulated from other conductive layers by a dielectric material. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to increased variations in a surface topography of the wafer. In other applications, metallization line patterns are formed into the dielectric material, and then metal planarization operations are performed to remove excess metallization.
The CMP process is one method for performing wafer planarization. In general, the CMP process involves holding and contacting a rotating wafer against a moving polishing pad under a controlled pressure. CMP systems typically configure the polishing pad on a rotary table or a linear belt.
FIG. 1 is an illustration showing a linear CMP apparatus, in accordance with the prior art. The linear CMP apparatus includes a polishing pad 101 configured to rotate in a direction 105 around rollers 103. A platen 107 is disposed opposite a working surface of the polishing pad 101 to provide backing support to the polishing pad 101 during a CMP operation. A wafer carrier 109 is configured to hold and apply a wafer 111 to the working surface of the polishing pad 101 during the CMP operation. The wafer carrier 109 is attached to a spindle 123 that is capable of rotating in a direction 113 while simultaneously applying the wafer 111 to the polishing pad 101 with an appropriate force as indicated by an arrow 115. An air bearing 117 is utilized between the platen 107 and the polishing pad 101 to facilitate traversal of the polishing pad 101 across the platen 107. A slurry 119 is introduced onto and distributed over the working surface of the polishing pad 101 to facilitate and enhance the CMP operation. Additionally, a conditioner 121 is used to condition the working surface of the polishing pad 101 as it travels in the direction 105.
During the CMP operation, a coefficient of friction between the wafer 111 and the polishing pad 101 can significantly influence the CMP process results. However, a relationship between the coefficient of friction and other parameters affecting the CMP operation has not been sufficiently developed and utilized.
In view of the foregoing, there is a need for a method of determining and utilizing the relationship between the coefficient of friction and other parameters affecting the CMP operation.